The present invention relates to the field of signal communications and more particularly to high-speed transfer of information within and between integrated circuit devices using electrical signaling.
In modern electronic systems, data and control information are transferred between various subsystems using extremely short-lived electrical signals. For example, in high-speed memory systems, a data signal from a memory controller to a memory device may be valid at the input of the memory device for only a nanosecond or less; less time, in some cases, than the propagation time of the data signal on the signaling path between the memory controller and the memory device. In any such high-speed signaling system, the ability of the receiving device to sample the data signal at a precise instant within the valid data interval (the xe2x80x9cdata eyexe2x80x9d) is often a critical factor in determining how brief the data eye may be and, consequently, the overall data transfer rate of the system. Accordingly, any technique for more accurately controlling the sampling instant within the data eye generally permits faster data transfer and therefore higher signaling bandwidth.
FIG. 1 illustrates a prior art high-speed signaling system in which a strobe signal is transmitted on strobe line DQS to control the sampling of data signals transmitted on data lines, DQ0-DQN. Because the strobe signal is edge-aligned with the data signals when transmitted (i.e., the strobe signal transition coincides with the opening of the data eye) and the DQS line introduces nominally the same propagation delay as the DQ0-DQn lines, the strobe signal and data signals arrive at the receiving device at nearly the same time. A variable delay circuit 15 then delays the strobe signal by half the nominal duration of the data eye so that the delayed strobe signal transitions at the midpoint of the data eye.
In order to prevent the delayed strobe signal from drifting away from the midpoint of the data eye (e.g., due to changes in voltage and temperature), a delay-locked loop circuit (DLL) 12 is provided to adjust the delay applied by the variable delay circuit over time. A variable delay circuit 21 within the DLL is formed by coarse and fine delay elements that correspond to coarse and fine delay elements within the variable delay circuit 15 in the strobe signal path. As the output of the variable delay circuit 21 within the DLL drifts out of phase with a reference clock signal (e.g., due to changes in voltage and temperature), the phase difference is detected by a phase detector 18 which outputs a signal to a delay control circuit 20 to adjust the delay control value applied to the variable delay circuit 21. The adjustment to the delay control value results in adjustment in the number of coarse and/or fine delay elements in the signal path of the variable delay circuit 21 so as to drive the output of the variable delay circuit 21 back toward phase lock with the reference clock signal. As shown in FIG. 1, the delay control value is also provided, after translation in a ratio circuit 22 according to the ratio between the reference clock period and one half the data eye duration, to the variable delay circuit 15 in the strobe signal path. By this arrangement, the delay applied to the data strobe signal is automatically adjusted to compensate for variations in voltage and temperature. Other relatively constant sources of error (e.g., process variations, mismatches in the DQS and DQ paths, etc.) may be compensated by the initial selection of coarse and fine delay elements within the variable delay circuit 21.
Unfortunately, because a delayed version of the data strobe signal is ultimately used to control the sampling of the DQ lines (a technique referred to herein as direct strobing), any transient sources of timing error in the data strobe signal such as intersymbol interference (ISI) and cross-talk, or data-dependent timing errors resulting from mismatched rising and falling edge rates are not significantly compensated by the variable delay circuit 15 and instead appear as timing jitter at the sample control inputs of the data receiver. This phenomenon is illustrated in FIG. 2. As shown, a strobe signal 31 is delayed by an amount of time, TEYE/2, to produce a delayed strobe signal 33 that transitions at the midpoint of the data eye. Slightly advanced and delayed versions of the strobe signal 31 resulting from transient sources of timing error are illustrated by dashed lines 34 and 35, respectively. Because the transient sources of timing error are passed through to the output of the variable delay circuit 15 of FIG. 1, the delayed strobe signal 33 is likewise advanced or delayed, resulting in a sampling point that is offset from the ideal sampling point as shown. As discussed above, such inaccuracy in the sampling point translates to lost timing margin and ultimately to reduced data transfer rates.
In accordance with an aspect of the present invention, an apparatus is disclosed that can reduce sampling errors for data communicated between devices. The apparatus uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty-percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.